Smoothing circuit

ABSTRACT

A smoothing circuit for realizing the miniaturization and the increase of integration scale of a circuit and for easily varying attack time and release time. This smoothing circuit comprises a capacitor, voltage comparator, charging circuit, and discharging circuit. The voltage comparator compares the terminal voltage of the capacitor with its input voltage and actuates the charging circuit or the discharging circuit according to a comparison result. The charging circuit charges the capacitor by intermittently supplying charging current. The discharging circuit discharges the capacitor by allowing discharging current to flow intermittently.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a smoothing circuit used in anAGC (automatic gain control) circuit or the like for a receiver.

[0003] 2. Description of the Related Art

[0004] An AGC circuit is used for control of the input signal level inAM receivers, FM receivers, and the like. In this AGC circuit, a signalis formed which changes gradually so as to follow a change in signallevel when the signal level changes, and a smoothing circuit is used toform such a signal.

[0005]FIG. 8 is a circuit diagram showing the configuration of aconventional smoothing circuit. The smoothing circuit shown in FIG. 8 isformed by combining two resistors 100 and 102 and a capacitor 104. Whenan input voltage is applied to one end of the resistor 100, a chargingcurrent flows into the capacitor 104 through the resistor 100 and theterminal voltage of the capacitor 104 is thereby increased. If theresistance value of the resistor 100 is R1 and the electrostaticcapacity of the capacitor 104 is C, time t1 during which the terminalvoltage of the capacitor 104 increases to a predetermined value can beexpressed by R1×C. This time t1 is an attack time. Time t1 is set toabout 10 to 50 msec in a smoothing circuit used in an AGC circuit for areceiver or the like.

[0006] When application of the input voltage to the one end of theresistor 100 is stopped, the capacitor 104 is discharged through theresistor 102 and the terminal voltage of the capacitor 104 is therebyreduced. If the resistance value of the resistor 102 is R2, time t2during which the terminal voltage of the capacitor 104 decreases to apredetermined value can be expressed by R2×C. This time t2 is a releasetime. Time t2 is set to about 200 to 500 msec in a smoothing circuitused in an AGC circuit for a receiver or the like.

[0007] The above-described conventional smoothing circuit has a problemthat in the case of realizing an attack time of about 10 to 50 msec anda release time of about 200 to 500 msec, the device constant of each ofthe resistors 100 and 102 and the capacitor 104 is so increased that itis difficult to limit the size of the circuit or to form the circuit inan IC, because it is necessary to set a large time constant in each ofthe combination of the resistor 100 and the capacitor 104 and thecombination of the resistor 102 and the capacitor 104. For example, inthe case of formation in an IC, the resistance value of the resistoractually formable is at most about 500 kΩ. If such a resistor is usedand if the release time t2 is set to 100 msec, C=t2/R2=0.2 μF. However,the electrostatic capacity of a capacitor in an IC according to a designconsidering the manufacturing cost, etc., is 20 pF or less. After all,it is difficult to form the entire smoothing circuit in an IC, and thecapacitor heretofore used is an externally-mounted large capacitor.

SUMMARY OF THE INVENTION

[0008] The present invention has been created in consideration of theabove-described points, and an object of the present invention is toprovide a smoothing circuit which can be reduced in size and formed inan IC.

[0009] Another object of the present invention is to provide a smoothingcircuit in which the attack time and the release time can be easily setto different lengths of time.

[0010] A smoothing circuit in accordance with the present invention hasa capacitor, a voltage comparator which compares a terminal voltage ofthe capacitor and an input voltage, a charging circuit whichintermittently charges the capacitor when the input voltage isrelatively higher than the terminal voltage, and a discharging circuitwhich intermittently releases a discharging current from the capacitorwhen the terminal voltage is relatively lower than the input voltage.Since the capacitor is intermittently charged and discharged, theterminal voltage of the capacitor changes gradually and an equivalentlylarge time constant can be set even if the electrostatic capacity of thecapacitor is reduced. Therefore, even in the case of setting a largetime constant, a smaller capacitor can be used and the size of thecircuit can be reduced. The need for a large resistor and a largecapacitor necessary for setting a large time constant is eliminated tomake it possible to reduce or completely remove externally mountedcomponent parts. Therefore, the entire smoothing circuit or almost allthe components parts can be formed in an IC.

[0011] It is desirable that the above-described charging circuitcomprises a current supply section which supplies a predeterminedcharging current to the capacitor, and a first timing control sectionwhich controls the timing of the operation to intermittently supply thecharging current by the current supply section. The operation tointermittently charge the capacitor can be easily controlled bycontrolling the timing of the operation to supply the charging currentby the current supply section.

[0012] It is desirable that the above-described first timing controlsection has a switch for performing the timing control on the basis of apulse signal having a predetermined duty ratio. The operation to supplythe charging current by the current supply section is controlled byturning on and off the switch according to the pulse signal, therebyenabling the charging speed or the like to be easily changed by changingthe period or the duty ratio of the pulse signal.

[0013] It is desirable that the above-described current supply sectioncomprises a constant-current circuit and a current mirror circuit whichsupplies the capacitor with the charging current equal to the currentgenerated by the constant-current circuit. Use of the current mirrorcircuit makes it possible to reliably supply the capacitor with thecharging current equal to the constant current generated by theconstant-current circuit and to stabilize the capacitor chargingoperation.

[0014] It is desirable that the above-described discharging circuitcomprises a current release section which releases the predetermineddischarging current fromthe capacitor, and a second timing controlsection which controls the timing of the operation to intermittentlyrelease the discharging current by the current release section. Theoperation to intermittently discharge the capacitor can be easilycontrolled by controlling the timing of the operation to release thedischarging current by the current release section.

[0015] It is desirable that the above-described second timing controlsection comprises a switch for performing the timing control on thebasis of a pulse signal having a predetermined duty ratio. The operationto release the discharging current by the current release section iscontrolled by turning on and off the switch according to the pulsesignal, thereby enabling the discharging speed or the like to be easilychanged by changing the period or the duty ratio of the pulse signal.

[0016] It is desirable that the above-described current release sectioncomprises a constant-current circuit and a current mirror circuit whichreleases from the capacitor the discharging current equal to the currentgenerated by the constant-current circuit. Use of the current mirrorcircuit makes it possible to reliably release the discharging currentequal to the constant current generated by the constant-current circuitfrom the capacitor and to stabilize the capacitor discharging operation.

[0017] In a case where the charging circuit comprises a current supplysection which supplies a predetermined charging current to thecapacitor, and a first timing control section which controls the timingof the operation to intermittently supply the charging current by thecurrent supply section, and where the discharging circuit comprises acurrent release section which releases the predetermined dischargingcurrent from the capacitor, and a second timing control section whichcontrols the timing of the operation to intermittently release thedischarging current by the current release section, it is desirable thatthe timing of supply of the charging current controlled by the firsttiming control section and the timing of discharging by the dischargingcurrent controlled by the second timing control section do not overlapeach other. The timings of charging and discharging of the capacitor aremade different from each other to enable the operation to charge thecapacitor and the operation to discharge the capacitor to be performedwith reliability.

[0018] It is desirable that the smoothing circuit further comprisescharging/discharging speed setting unit for setting the speed ofcharging by the charging circuit and the speed of discharging by thedischarging circuit to different values. If the charging/dischargingspeed setting unit is provided, the speed of charging of the capacitorand the speed of discharging of the capacitor can b set different fromeach other, thus making it possible to easily realize a smoothingcircuit in which the attack time and release time can easily be set todifferent lengths of time.

[0019] It is desirable that the charging circuit comprises a currentsupply section which supplies a predetermined charging current to thecapacitor, and a first timing control section which controls the timingof the operation to intermittently supply the charging current by thecurrent supply section; the discharging circuit comprise a currentrelease section which releases the predetermined discharging currentfrom the capacitor, and a second timing control section which controlsthe timing of the operation to intermittently release the dischargingcurrent by the current release section; and the timings of intermittentsupply of the charging current and intermittent release of thedischarging current by the first and second timing control sections bemade different from each other by the charging/discharging speed settingunit. The operation to intermittently discharge the capacitor can easilybe controlled by controlling the timing of the operation to supply thecharging current by the current supply section and the timing of theoperation to release the discharging current by the current releasesection. Moreover, the attack time and the release time can easily beset to different lengths of time by setting the time periods forcharging and discharging different from each other.

[0020] In the case where each of the first and second timing controlsections has a switch for performing timing control on the basis of apulse signal having a predetermined duty ratio, it is desirable that theabove-described charging/discharging speed setting unit sets the dutyratio of the pulse signal for charging and the duty ratio of the pulsesignal for discharging to different values. The control for setting thecharging time and the discharging time to different lengths of time isthereby facilitated.

[0021] It is desirable that the charging/discharging speed setting unitsets the charging current supplied by the current supply section and thedischarging current released by the current release section to differentvalues. The attack time and the release time can easily be set todifferent lengths of time by setting the charging current and thedischarging current to different values.

[0022] In a case where each of the current supply section and thecurrent release section is constituted by a transistor having apredetermined reference voltage applied to its gate, it is desirablethat the charging/discharging speed setting unit makes the gate size ofthe transistor for charging and the gate size of the transistor fordischarging different from each other. The control for setting thecharging current and the discharging current to different values isthereby facilitated.

[0023] It is desirable that the frequency of the pulse signal forsetting the above-described charging and discharging timings be higherthan twice the frequency of the input signal. Accurate sampling of thewaveform of the input signal can be ensured by setting the frequency ofth pulse signals higher than twice the frequency of the input signal. Ifthe frequency of the pulse signals is set to twice the frequency of theinput signal, coincidence with the time at which the amplitude of theinput signal becomes zero may occur to cause failure to perform theoperation on the basis of the waveform of the input signal. If thefrequency of the pulse signals is set lower than twice the frequency ofthe input signal, there is a possibility of no pulse signal being outputduring the half-wavelength period of the waveform of the input signal,resulting in failure to perform the smoothing operation with accuracy onthe basis of the waveform of the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a block diagram of the principle of a smoothing circuitin a first embodiment;

[0025]FIG. 2 is a configuration diagram showing an example of use of asmoothing circuit included in an AGC circuit;

[0026]FIG. 3 is a circuit diagram showing a concrete configuration ofthe smoothing circuit;

[0027]FIG. 4 is a block diagram of the principle of a smoothing circuitin a second embodiment;

[0028]FIG. 5 is a circuit diagram showing a concrete configuration ofthe smoothing circuit;

[0029]FIG. 6 is a circuit diagram showing an example of a modificationof the smoothing circuit;

[0030]FIG. 7 is a diagram showing the gate size of a MOS transistor; and

[0031]FIG. 8 is a circuit diagram showing the configuration of aconventional smoothing circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] A smoothing circuit to which the present invention is appliedaccording to an embodiment of the present invention will be describedwith reference to the drawings.

[0033] (First Embodiment)

[0034]FIG. 1 is a block diagram of the principle of a smoothing circuitin a first embodiment of the present invention. As shown in FIG. 1, thesmoothing circuit of this embodiment has a capacitor 10, a voltagecomparator 12, a charging circuit 14, and a discharging circuit 16. Thevoltage comparator 12 compares a terminal voltage of the capacitor 10and an input voltage with each other and makes effective the operationof the charging circuit 14 or the discharging circuit 16 according tothe result of this comparison. The charging circuit 14 charges thecapacitor 10 by intermittently supplying a charging current. Forexample, this charging circuit 14 comprises a constant-current circuitand a switch. When the switch becomes ON, the charging current issupplied from the constant-current circuit to the capacitor 10. Thedischarging circuit 16 discharges the capacitor 10 by causing adischarging current to flow intermittently. For example, thisdischarging circuit 16 comprises a constant-current circuit and aswitch. Wh n the switch becomes ON, a constant current is released fromthe capacitor 10.

[0035] Thus, the smoothing circuit of this embodiment performsintermittent charging and discharging operations on the capacitor 10.Therefore, even in a case where the electrostatic capacity of thecapacitor 10 is set small, the opposite-terminal voltage of thecapacitor 10 changes gradually and charging and dischargingcharacteristics can be obtained which are equivalent to those obtainedin the case of use of a circuit having a large time constant, i.e., acapacitor having a large electrostatic capacity and a resistor having alarge resistance value. The charging circuit 14 and the dischargingcircuit 16, which control supply of the predetermined current to thecapacitor 10 and release of the predetermined current from the capacitor10, are capable of setting the current values to substantially largevalues suitable for formation in an IC because they perform supply andrelease operations intermittently. Therefore the entire smoothingcircuit can be formed in an IC. Since the need for an externally mountedcomponent such as a capacitor is eliminated, the overall size of thesmoothing circuit can be effectively reduced.

[0036] A concrete example of the configuration of the above-describedsmoothing circuit of this embodiment and an example of application ofthe smoothing circuit will next be described.

[0037]FIG. 2 is a configuration diagram showing an example of use of asmoothing circuit included in an AGC circuit. FIG. 2 shows part of theconfiguration of an AGC circuit which performs gain control in areceiver according to the intensity of an electric field. The receivermay be a direct-conversion receiver, a superheterodyne receiver or thelike.

[0038] Referring to FIG. 2, an amplitude detection circuit 20 issupplied with a carrier signal in the receiver and performs half-wave orfull-wave rectification on the input carrier signal. A capacitor 22 isfor removing the carrier portion of the signal after rectification bythe amplitude detection circuit 20. If the carrier portion is removed bythe capacitor 22, and if the carrier is not amplitude modulated, adirect current voltage can be obtained and, therefore, a smoothingcircuit 24 in a following stage is unnecessary. However, AM waves andeven FM waves have some amplitude change and the smoothing circuit 24 isrequired if it is necessary to detect the intensity of the receivedelectric field.

[0039] The smoothing circuit 24 smoothes the voltage level of a signalfrom which the carrier portion has been removed by the capacitor 22. Thesmoothed voltage is applied to a buffer 26 having a high inputimpedance. A control DC signal necessary for AGC operation is outputfrom this buffer 26.

[0040]FIG. 3 is a circuit diagram showing a concrete example of aconfiguration of the smoothing circuit 24. As shown in FIG. 3, thesmoothing circuit 24 comprises a capacitor 10, a constant-currentcircuit 40, transistors 42, 44, 50, 54, and 56, switches 46 and 52, avoltage comparator 60, and AND circuits 62 and 64.

[0041] Two transistors 42 and 44 constitute a current mirror circuit togenerate a charging current equal to a constant current output from theconstant-current circuit 40. The timing of generation of this chargingcurrent is determined by the switch 46.

[0042] The switch 46 is constituted by an inverter circuit 1, an analogswitch 2, and a transistor 3. The analog switch 2 is formed byconnecting a p-channel transistor and an n-channel transistor betweentheir sources and drains in parallel. An output signal from the ANDcircuit 62 is directly input to the gate of the n-channel transistor,while a signal obtained by inverting the logic of this output signal bythe inverter circuit 1 is input to the gate of the p-channel transistor.Therefore this analog switch 2 is on when the output signal from the ANDcircuit 62 is high level, and is off when the output signal from the ANDcircuit 62 is low level. The transistor 3 is for establishing alow-resistance connection between the gate and the drain of thetransistor 44when the analog switch 2 is off. A current supply operationwith the transistor 44 is thereby stopped with reliability.

[0043] When the switch 46 becomes on, the gate of the transistor 42 onone side to which the constant-current circuit 40 is connected and thegate of the transistor 44 on the other side are in a state of beingconnected to each other. In this state, therefore, a current which issubstantially the same as a constant current generated by theconstant-current circuit 40 connected to the transistor 42 on one sideis also caused to flow through the path between the source and drain ofthe transistor 44 on the other side. This current is supplied as acharging current to the capacitor 10. Conversely, when the switch 46becomes off, the gate of the transistor 44 is connected to the drain tostop supplying the charging current.

[0044] The above-described constant-current circuit 40 and twotransistors 42 and 44 correspond to the current supply section. Theswitch 46 and the AND circuit 62 correspond to the first timing controlsection.

[0045] The current mirror circuit with which a discharging current tothe capacitor 10 is set is formed by combining a transistor 50 with theabove-described transistor 42 and constant-current circuit 40, and theoperating state of the current mirror circuit is determined by theswitch 52. The switch 52 has the same configuration as that of theswitch 46. The on/off state of the switch 52 is controlled according tothe logic of an output signal from the AND circuit 64. The switch 52 isin the on state when this output signal is high level, and in the offstate when this output signal is low level.

[0046] When the switch 52 is in the on state, the gate of the transistor42 on one side to which the constant-current circuit 40 is connected andthe gate of the transistor 50 on the other side are in a state of beingconnected to each other. In this state, therefore, a current which issubstantially the same as the constant current generated by theconstant-current circuit 40 is also caused to flow through the pathbetween the source and drain of the transistor 50 on the other side.This current is a discharging current by which charge accumulated in thecapacitor 10 is released.

[0047] However, the current flowing through the transistor 50 cannot beextracted directly from the capacitor 10. In this embodiment, therefore,another current mirror circuit constituted by transistors 54 and 56 isconnected on the source side of the transistor 50.

[0048] The two transistors 54 and 56 have their gates connected to eachother. When the above-described discharging current flows through thetransistor 54, the same current also flows through the path between thesource and the drain of the other transistor 56. This transistor 56 hasits drain connected to the terminal of the capacitor 10 on thehigh-potential side and the current flowing through the transistor 56 isgenerated by release of charge accumulated in the capacitor 10.

[0049] The above-described constant-current circuit 40 and the fourtransistors 42, 50, 54, and 56 correspond to the current releasesection. The switch 52 and the AND circuit 64 correspond to the secondtiming control section.

[0050] The voltage comparator 60 compares the magnitude of the terminalvoltage of the capacitor 10 applied to its plus terminal and themagnitude of the input voltage of the smoothing circuit 24 applied toits minus terminal. The voltage comparator 60 has a noninverting outputterminal and an inverting output terminal. When the terminal voltage ofthe capacitor 10 applied to the plus terminal is higher than the inputvoltage applied to the minus terminal, the voltage comparator 60 outputsa high-level signal through the noninverting output terminal and outputsa low-level signal through the inverting output terminal. Conversely,when the terminal voltage of the capacitor 10 applied to the plusterminal is lower than the input voltage applied to the minus terminal,the voltage comparator 60 outputs a low-level signal through thenoninverting output terminal and outputs a high-level signal through theinverting output terminal.

[0051] A predetermined pulse signal is input to the AND circuit 62through one of two input terminals of the AND circuit 62, and thenoninverting input terminal of the voltage comparator 60 is connected tothe other of the input terminals of the AND circuit 62. Therefore thepredetermined pulse signal is output from the AND circuit 62 when theterminal voltage of the capacitor 10 is higher than the input voltage ofthe smoothing circuit 24.

[0052] Also, a predetermined pulse signal is input to the AND circuit 64through one of two input terminals of the AND circuit 64, and theinverting input terminal of the voltage comparator 60 is connected tothe other of the input terminals of the AND circuit 64. Therefore thepredetermined pulse signal is output from the AND circuit 64 when theterminal voltage of the capacitor 10 is lower than the input voltage ofthe smoothing circuit 24.

[0053] The smoothing circuit 24 is thus arranged. The operation of thesmoothing circuit 24 will next be described.

[0054] In the case where the capacitor 10 is not in a charged state orthe input voltage of the smoothing circuit 24 is increasing when thesmoothing circuit 24 starts operating, the terminal voltage of thecapacitor 10 is lower than the input voltage of the smoothing circuit24. In this state, the pulse signal is output from the AND circuit 62,while no pulse signal is output from the AND circuit 64. Accordingly,only the switch 46 is intermittently set in the on state. Each time theswitch 46 is in the on state, the predetermined charging current issupplied to the capacitor 10. This charging operation is continued untilthe terminal voltage of the capacitor 10 becomes higher relatively thanthe input voltage of the smoothing circuit 24.

[0055] When the terminal voltage of the capacitor 10 exceeds the inputvoltage of the smoothing circuit 24 as a result of this chargingoperation, or when the input voltage is decreasing and lower than theterminal voltage of the capacitor 10, the pulse signal is output fromthe AND circuit 64, while no pulse signal is output from the AND circuit62. Accordingly, only the switch 52 is intermittently set in the onstate. Each time the switch 52 is in the on state, the predetermineddischarging current is caused to flow out of the capacitor 10. Thisdischarging operation is continued until the terminal voltage of thecapacitor 10 becomes lower relatively than the input voltage of thesmoothing circuit 24.

[0056] It is necessary that in the above-described smoothing circuit 24the frequency of the pulse signals for setting the timings of chargingand discharging of the capacitor 10 (the pulse signals output from theAND circuit 62 or 64) be set to a value higher than twice the frequencyof the input signal input through the noninverting input terminal of thevoltage comparator 60. This setting ensures that the smoothing operationcan be performed by sampling the waveform of the input signal withaccuracy. If the frequency of the pulse signals is set to twice thefrequency of the input signal, coincidence with the time at which theamplitude of the input signal becomes zero may occur to cause failure toperform the operation on the basis of the waveform of the input signal.If the frequency of the pulse signals is set lower than twice thefrequency of the input signal, there is a possibility of no pulse signalbeing output during the half-wavelength period of the waveform of theinput signal, resulting in failure to perform the smoothing operationwith accuracy on the basis of the waveform of the input signal.

[0057] It is also necessary to set the two kinds of pulse signal forsetting the timings of charging and discharging of the capacitor 10 sothat the output timings do not overlap each other. By setting thetimings of charging and discharging of the capacitor 10 different fromeach other, it is ensured that the operation to charge the capacitor 10and the operation to discharge the capacitor 10 can be performed withreliability.

[0058] (Second Embodiment)

[0059] In the smoothing circuit 24 of which a concrete example of theconfiguration is shown in FIG. 3, the period and the duty ratio of thepulse signal for determining the timing of supply of the chargingcurrent and the period and the duty ratio of the pulse signal fordetermining the timing of supply of the discharging current are setequal to each other. However, they may differ from each other. Forexample, the duty ratio of the pulse signal input to the AND circuit 64shown in FIG. 3 is set lower than the duty ratio of the pulse signalinput to the AND circuit 62. In this manner, the release time can be setlonger than the attack time.

[0060]FIG. 4 is a block diagram of the principle of a smoothing circuitin a second embodiment of the present invention. As shown in FIG. 4, asmoothing circuit 124 of this embodiment has a capacitor 10, a voltagecomparator 12, a charging circuit 14, a discharging circuit 16, and acharging/discharging speed setting section 18. The smoothing circuitshown in FIG. 4 differs from the smoothing circuit of the firstembodiment shown in FIG. 1 in that the charging/discharging speedsetting section 18 is added.

[0061] The charging/discharging speed setting section 18 makes such asetting that the speed of charging of the capacitor 10 by the chargingcircuit 14 and the speed of discharging of the capacitor 10 by thedischarging circuit 16 differ from each other. The charging/dischargingspeed setting section 18 corresponds to the charging/discharging speedsetting unit. Detailed description of the charging/discharging speedsetting section 18 will be made below.

[0062] In the smoothing circuit of this embodiment, thecharging/discharging speed setting section 18 sets the speed of chargingof the capacitor 10 and the speed of discharging of the capacitor 10different from each other. Therefore the attack time and the releasetime in the case of use of this smoothing circuit in an AGC circuit orthe like can be made different from each other.

[0063]FIG. 5 is a circuit diagram showing a concrete configuration ofthe smoothing circuit 124. As shown in FIG. 5, the smoothing circuit 124comprises a capacitor 10, a constant-current circuit 40, transistors 42,44, 50, 54, and 56, switches 46 and 52, a voltage comparator 60, ANDcircuits 62 and 64, and a frequency divider 70. The smoothing circuit124 shown in FIG. 5 has such a configuration that the frequency divider70 corresponding to the charging/discharging speed setting section 18(charging/discharging speed setting unit) is added to the smoothingcircuit 24 of the first embodiment shown in FIG. 3. Components basicallythe same as those in the smoothing circuit 24 shown in FIG. 3 areindicated by the same reference numerals, and detailed description ofthem will not be repeated.

[0064] The frequency divider 70 divides at a predetermined divisionratio the frequency of the pulse signal input to the AND circuit 62through one of the two input terminals of the AND circuit 62, andoutputs the frequency-divided signal. The predetermined pulse signaloutput from the frequency divider 70 is input to the AND circuit 64through one of two input terminals of the AND circuit 64, and theinverting output terminal of the voltage comparator 60 is connected tothe other of the input terminals of the AND circuit 64, thereby enablingthe predetermined pulse signal to be output from the AND circuit 64 whenthe terminal voltage of the capacitor 10 is lower than the input voltageof the smoothing circuit 124.

[0065] In two kinds of pulse signal output from the two AND circuits 62and 64, the duty ratio of the pulse signal output from the AND circuit62 is higher than the duty ratio of the pulse signal output from the ANDcircuit 64. Therefore, if pulse signals are respectively output from thetwo AND circuits 62 and 64 for the same time period, the speed ofcharging per unit time period is higher than that of discharging.Consequently, the attack time is shorter than the release time.

[0066] In this embodiment, only one of the two output terminals of thevoltage comparator 60 is high level. Therefore there is no possibilityof the pulse signals being simultaneously output from the two ANDcircuits 62 and 64, and the operation to charge or discharge thecapacitor 10 can be performed with reliability and safety.

[0067] The present invention is not limited to the above-describedembodiments, and various modifications can be made in the embodimentswithout departing from the scope of the gist of the present invention.For example, while in the above-described second embodiment thefrequency divider 70 is used to output from the two AND circuits 62 and64 pulse signals having duty ratios different from each other, pulsesignals having different duty ratios may be separately formed andrespectively input to the two AND circuits 62 and 64. However, it isnecessary to avoid simultaneously inputting the two kinds of pulsesignals separately generated to the two AND circuits 62 and 64. If thereis a possibility of the pulse signals being simultaneously input, ablocking circuit for forcibly blocking input of one of the pulse signalsmay be provided.

[0068] In the above-described second embodiment, the proportions of thetime periods in the unit time during which the transistors 44 and 50 arerespectively set in the on states are set to different values in orderto perform charging and discharging of the capacitor 10 at differentspeeds. Alternatively, the gate sizes of these transistors may be madedifferent from each other to set the charging current and thedischarging current to different values.

[0069]FIG. 6 is a circuit diagram showing an example of a modificationof the smoothing circuit. A smoothing circuit 124A shown in FIG. 6differs from the smoothing circuit 124 shown in FIG. 5 in that thefrequency divider 70 is removed and the two transistors 44 and 50 arereplaced with two transistors 44A and 50A having the gate sizes changed.

[0070]FIG. 7 is a diagram showing the gate size of a MOS transistor(FET). Even when the gate voltage is fixed, the channel resistance canbe changed by selecting the gate width W and the gate length L to changethe current flowing through the path between the source and the drain.In this example of modification, in order to shorten the attack time byincreasing the charging current, the gate width W of the transistor 44Ais set to a larger value and the gate length L is set to a smallervalue. On the other hand, in order to increase the release time byreducing the discharging current, the gate width W of the transistor 50Ais set to a smaller value and the gate length L is set to a largervalue. Thus, it is also possible to easily set different lengths of timeas attack time and release time by changing the gate size of each of thetransistors 44A and 50A. In this case, the transistors 44A and 50Aconstitute portions of the charging circuit 14 and the dischargingcircuit 16 and function as the charging/discharging speed setting unit.

INDUSTRIAL APPLICABILITY

[0071] According to the present invention, as described above, thecapacitor is intermittently charged and discharged, so that the terminalvoltage of the capacitor changes gradually and an equivalently largetime constant can be set even if the electrostatic capacity of thecapacitor is reduced. Therefore, even in the case of setting a largetime constant, a smaller capacitor can be used and the size of thecircuit can be reduced. The need for a large resistor and a largecapacitor necessary for setting a large time constant is eliminated tomake it possible to reduce or completely remove externally mountedcomponent parts. Therefore, the entire smoothing circuit or almost allthe components parts can be formed in an IC. Further, thecharging/discharging speed setting unit is provided to set the speeds ofcharging and discharging of the capacitor to different values. It is,therefore, possible to realize a smoothing circuit in which differentlengths of time can easily set as attack time and release time.

What is claimed is:
 1. A smoothing circuit comprising: a capacitor; a voltage comparator which compares a terminal voltage of said capacitor and an input voltage; a charging circuit which intermittently charges said capacitor when said input voltage is higher relatively than said terminal voltage; and a discharging circuit which intermittently releases a discharging current from said capacitor when said terminal voltage is lower relatively than said input voltage.
 2. The smoothing circuit according to claim 1 wherein said charging circuit comprises a current supply section which supplies a predetermined charging current to said capacitor, and a first timing control section which controls the timing of the operation to intermittently supply the charging current by said current supply section.
 3. The smoothing circuit according to claim 2 wherein said first timing control section has a switch for performing said timing control on the basis of a pulse signal having a predetermined duty ratio.
 4. The smoothing circuit according to claim 3 wherein the frequency of said pulse signal is higher than twice the frequency of the input signal.
 5. The smoothing circuit according to claim 2 wherein said current supply section comprises a constant-current circuit and a current mirror circuit which supplies said capacitor with the charging current equal to the current generated by said constant-current circuit.
 6. The smoothing circuit according to claim 1 wherein said discharging circuit comprises a current release section which releases the predetermined discharging current from said capacitor, and a second timing control section which controls the timing of the operation to intermittently release the discharging current by said current release section.
 7. The smoothing circuit according to claim 6 wherein said second timing control section has a switch for performing said timing control on the basis of a pulse signal having a predetermined duty ratio.
 8. The smoothing circuit according to claim 7 wherein the frequency of said pulse signal is higher than twice the frequency of the input signal.
 9. The smoothing circuit according to claim 6 wherein said current release section comprises a constant-current circuit and a current mirror circuit which releases from said capacitor the discharging current equal to the current generated by said constant-current circuit.
 10. The smoothing circuit according to claim 1 wherein said charging circuit comprises a current supply section which supplies a predetermined charging current to said capacitor, and a first timing control section which controls the timing of the operation to intermittently supply the charging current by said current supply section; said discharging circuit comprises a current release section which releases the predetermined discharging current from said capacitor, and a second timing control section which controls the timing of the operation to intermittently release the discharging current by said current release section; and the timing of supply of the charging current controlled by said first timing control section and the timing of discharging by the discharging current controlled by said second timing control section do not overlap each other.
 11. The smoothing circuit according to claim 1, further comprising charging/discharging speed setting unit for setting the speed of charging by said charging circuit and the speed of discharging by said discharging circuit to different values.
 12. The smoothing circuit according to claim 11 wherein said charging circuit comprises a current supply section which supplies a predetermined charging current to said capacitor, and a first timing control section which controls the timing of the operation to intermittently supply the charging current by said current supply section; said discharging circuit comprises a current release section which releases the predetermined discharging current from said capacitor, and a second timing control section which controls the timing of the operation to intermittently release the discharging current by said current release section; and said charging/discharging speed setting unit sets different lengths of time as the time period for intermittent supply of the charging current controll d by said first timing control section and the time period for intermittent release of the discharging current controlled by said second timing control section.
 13. The smoothing circuit according to claim 12, wherein said first and second timing control sections each have a switch for performing said timing control on the basis of a pulse signal having a predetermined duty ratio; and wherein said charging/discharging speed setting unit sets the duty ratio of said pulse signal for charging and the duty ratio of said pulse signal for discharging to different values.
 14. The smoothing circuit according to claim 12, wherein said charging/discharging speed setting unit sets the charging current supplied by said current supply section and the discharging current released by said current release section to different values.
 15. The smoothing circuit according to claim 14, wherein each of said current supply section and said current release section is constituted by a transistor having a predetermined reference voltage applied to its gate; and said charging/discharging speed setting unit makes the gate size of said transistor for charging and the gate size of said transistor for discharging different from each other.
 16. The smoothing circuit according to claim 13 wherein the frequency of said pulse signal is higher than twice the frequency of the input signal. 